Project C01 - UWB Phase-Locked Loops with Highest Phase Stability
Principal Investigator: Prof. Dr.-Ing. Thomas Musch, RUB
Achieved results and methods
One highlight of the achievements in C01 is the novel YTO [5],[6] with several methods and results. The main idea is to directly mount the Yttrium-Iron-Garnet (YIG) sphere over a Monolithic Microwave Integrated Circuit (MMIC), including the amplifier, and use crossed chip-to-chip bond wires to couple the YIG, as depicted in Fig. 1. This enables realizing a transmission-type YTO at high oscillation frequencies.
In the 2nd phase a further optimized MMIC was developed with less parasitic capacitance to increase the oscillator’s bandwidth to 30 GHz. It now operates from 18 GHz to 48 GHz with a sufficiently high output power as depicted in Fig. 1. Furthermore, the crossed chip-to-chip bonding was improved in two ways. On the one hand, a thicker wire was used which reduces the losses in the oscillator’s core. Thus the phase noise is significantly improved compared to the already published ones [2], [4]. On the other hand, the newly used ball-wedge bonds provide a better shape of the wire which increases the reproducibility of the measurements and simplifies the manufacturing.
The YTO’s MMIC and circuit are mounted within the air gap of a cobalt iron alloy magnetic core to achieve magnetization up to 1.7 T, which corresponds to an oscillation frequency of 48 GHz. The advantage of the cobalt iron alloy is its linear magnetizability. Most other magnetic materials saturate at much lower magnetic fields of less than one tesla. A linear frequency ramp would therefore not be feasible. The YTO requires highly customized magnetic coils with customized coil shells. A stereolithography process was used to create complex, stable, and temperature-resistant coil shells. Coil winding tools were designed and manufactured. This made it possible to produce coils perfectly suited for use with YTO. The setup is shown in Fig. 1.
The Sapphire Loaded Cavity Oscillator (SLCO) is realized with its core resonator operating in a high mode (WGE9,0,1) to curtail the evanescent field leading to an enhancement of the quality factor. To ensure the operation in the desired mode, a technique for mode suppression utilizing microwave absorbers [7] was adapted in addition to the filtering realized in the 1st phase. Dielectric Resonator (DiR). The core resonator exceeds a loaded quality factor of Q = 80,000 at fSLCO = 19.69 GHz.
Hence, the natural susceptibility due to temperature deviation of the SLCO’s oscillation frequency, a concept was realized to ensure the operation of the core resonator with maximum quality factor at all times. It is achieved by utilizing a Pound-stabilization method, resulting in an autonomous and self-referencing phase regulation, optimizing the phase noise characteristics of the SLCO’s core resonator. The system is depicted in Fig. 2. Additionally, a method to 3D print the DiR’s cavity and metalize it with a combination of plasma sputtering and galvanization was investigated. Thus, the weight was reduced to several grams without impairment of the quality factor.
The most suitable concept for a frequency divider for C01 is a dual-modulus divider [3],[8]. In terms of programmability, operating speed, and additive phase noise [9], it is the most promising concept in contrast to 2/3-divider-cascades [10], synchronous, or asynchronous counters. Although the operating speed and the noise performance of the realized 8-bit frequency divider [3],[11] during the 1st phase are already outstanding, it is crucial to further improve this. In order to avoid the additive phase noise of the divider dominating the high-performance PLL’s noise, a detailed investigation of the design parameters’s influence on the performance was carried out in [12],[13]. The current densities of the transistors and the logical voltage swing of the used emitter-coupled logic with merged logic gates were investigated and optimized. Additionally, inductive peaking was applied. The result is the fastest, widest bandwidth dual modulus divider with the lowest phase noise reported to date [12]. As shown in Fig. 3, the divider operates up to 142 GHz which is in good agreement with the simulations.
For the additive phase noise measurements in Fig. 3, the three-converter method was applied which is the only method to ensure correct measurements but also requires high measurement effort. The measured noise results in an additional jitter between 500 as and 1.9 fs. A photograph of the additive phase noise measurement setup is shown in Fig. 3.
The initial approach for the chirp synthesizer utilized a frequency divider which is programmed with pre-calculated division ratios stored in RAM. To increase the insufficient bandwidth, this Binary Direct Digital Synthesizer (BDDS) should therefore be extended to a closed-loop concept. It turns out that recent FPGAs are not capable of using a wideband signal to synchronize the high-speed transceivers. Therefore, a completely novel concept was developed, realized, and measured [14].
A block diagram and a photograph of the novel and realized BDDS are shown in Fig. 4. The pre-calculated division ratios Mmod are saved in a fast DDR4 memory. The FPGA buffers the division ratios in an asynchronous FIFO. Synchronized with the reference SLCO, the FPGA’s output transceivers program the frequency divider M with MTX at a frequency fTX. To ensure proper functionality of the divider, MTX has to be set when the divider loads the new actual division ratio M. This is realized by an oversampling with fTX>>fmod, with the BDDS’s modulated output frequency fmod=fSLCO/Mmod. The oversampling is depicted in Fig. 5 for an example division ratio of 50 with Sigma-Delta Modulation (SDM). The concepts were realized and measured with output frequencies higher than 2.5 GHz. The power spectrum in Fig. 4 shows, that the measurements and simulations are in good agreement. A measured spectrogram of a complete ramp from 1.1 GHz to 1.46 GHz is shown in Fig. 5. Here the bandwidth is limited by the measurement equipment. The spectrogram shows the SDM noise which will be suppressed by the loop filter of the subsequent PLL. The ability to generate any ramp shape allows for pre-distortion, e.g. to reduce settling time [15].
One crucial step to using the YTO is the controlling for high-frequency chirps. The YTO’s output frequency fosc=γ·B is equal to the external magnetic field B generated by electromagnet multiplied by the gyromagnetic ratio of YIG γ = 28 GHz/T. By combining different types of inductors, a high electromagnetic field can be generated with simultaneously high controlling bandwidth as depicted in Fig. 6. Two big inductors can coarse-tune the magnetic field in the magnetic core with the YTO placed in the air gap (Fig. 1). This slow control (SC) is used to realize the frequency chirp from feasible 18 GHz to 48 GHz.
To reduce the noise of the YTO, a fast control (FC) inductor is utilized. A small air coil around the YTO MMIC is capable of tuning the YTO’s oscillation frequency over a bandwidth of several hundred megahertz. Furthermore, the loop filter for the SC includes an integrator allowing frequency chirps and eliminating slow frequency drifts due to temperature or non-linearity. Whereas the FC is realized without an integrator. Thus, it is utilized to reduce the noise for offset frequencies beyond the controlling frequency of the SC which is limited by the self-resonance of the big inductors.
Selected project-related publications